1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device and manufacturing method thereof, and more particularly, to a structure of a semiconductor integrated circuit device including an SRAM (Static Random Access Memory) and manufacturing method thereof.
2. Description of the Background Art
An SRAM has been known as a static-type semiconductor memory device. The most preferable effect of the present invention can be obtained when it is applied to the SRAM, and therefore, a conventional SRAM will now be described with reference to the figures.
Referring to FIGS. 25A to 25C, in a single memory cell, two driver transistors (n-channel MOS transistors) Q3 and Q4 with their gate electrodes and drain electrodes cross-coupled to each other, and two load transistors (p-channel MOS transistors) Q5 and Q6 connected to the drain electrodes of the driver transistors Q3 and Q4, respectively, constitute a flip-flop type memory cell. The drain electrodes of these two driver transistors Q3 and Q4 are connected to two access transistors (n-channel MOS transistors) Q1 and Q2, respectively. Gate electrodes of these access transistors Q1 and Q2 are connected to a word line WL. When this word line WL is selected, information held in driver transistors Q3 and Q4 is transferred to bit lines BLa and BLb through access transistors Q1 and Q2, respectively. One memory cell node N1 is connected to the drain electrode of driver transistor Q3, the gate electrode of driver transistor Q4, a drain electrode of load transistor Q5, and a gate electrode of load transistor Q6. The other memory cell node N2 is connected to the gate electrode of driver transistor Q3, the drain electrode of driver transistor Q4, a gate electrode of load transistor Q5, and a drain electrode of load transistor Q6. Source electrodes of driver transistors Q3 and Q4 are connected to a ground potential GND. Source electrodes of load transistors Q5 and Q6 are connected to a power supply potential Vcc.
A flip-flop circuit having to stable states is formed of driver transistors Q3 and Q4 with their drain electrodes and gate electrodes cross-connected to each other. Thus, bit information (data) can be recorded. More specifically, 1-bit information can be stored if potentials of one memory cell node N1 and the other N2 are held at a "High" level and a "Low" level or at "Low" and "High", respectively. When a desired memory cell is selected, that is, word line WL is at a "High" level, access transistors Q1 and Q2 are turned on. Thus, memory cell nodes N1 and N2 are rendered conductive with bit lines BLa and BLb, respectively. At this time, voltages corresponding to the states of driver transistors Q3 and Q4 appear at bit lines BLa and BLb through access transistors Q1 and Q2, respectively. Thus, information held in the memory cell is read out. When data is to be written into the memory cell, voltages corresponding to desired states to be written are applied to bit lines BLa and BLb, respectively, with access transistors Q1 and Q2 turned on. In order to maintain a data-stored state latched by the flip-flop circuit which is constituted by driver transistors Q3 and Q4, current is supplied from power supply potential Vcc through load transistors Q5 and Q6.
As described above, a memory cell of a CMOS type SRAM is constituted by six transistors Q1-Q6. Thus, as shown in FIG. 25B, a region where four n-channel MOS transistors are formed and a region where two p-channel MOS transistors are formed are required to form a single memory cell. In addition, as shown in FIG. 25C, a p-type well region and an n-type well region are required to form the n-channel MOS transistors and the p-channel MOS transistors in a semiconductor substrate. Thus, area which is required for the CMOS type SRAM memory cell is large so long as a bulk-type MOS transistor (an MOS transistor formed on a surface of a semiconductor substrate) is used. Accordingly, the CMOS type SRAM memory cell which is constituted by the bulk-type MOS transistor is not suitable for improving degree of integration.
A structure of an SRAM memory cell which solves the above-described problems and allows higher degree of integration includes a high resistance load type memory cell.
Referring to FIG. 26A, in a single memory cell, two driver transistors (n-channel MOS transistors) Q3 and Q4 having their gate electrodes and drain electrodes cross-coupled to each other, and two high resistance loads HR1 and HR2 connected to respective drain electrodes of the driver transistors constitute a flip-flop type memory cell. Two access transistors (n-channel MOS transistors) Q1 and Q2 are connected to the drain electrodes of these two driver transistors Q3 and Q4, respectively. Gate electrodes of these access transistors Q1 and Q2 are connected to a word line WL. When this word line WL is selected, information held in driver transistors Q3 and Q4 is transferred to bit lines BLa and BLb through access transistors Q1 and Q2, respectively. One memory cell node N1 is connected to the drain electrode of driver transistors Q3 and the gate electrode of driver transistor Q4. The other memory cell node N2 is connected to the gate electrode of driver transistor Q3 and the drain electrode of driver transistor Q4. The source electrodes of driver transistors Q3 and Q4 are connected to a ground potential GND. In addition, drain electrodes of driver transistors Q3 and Q4 are connected to a power supply potential Vcc through high resistance loads HR1 and HR2, respectively.
As in the case of the CMOS-type memory cell, in the high resistance load type memory cell with the above-described arrangement, a flip-flop circuit is formed with drain electrodes and gate electrodes of driver transistors Q3 and Q4 cross-connected to each other. Thus, bit information (data) can be stored. Read/write operation of data in the high resistance load-type memory cell is the same as that in the above-described CMOS-type memory cell. The high resistance load-type memory cell is different from the CMOS-type memory cell in that current is supplied from power supply potential Vcc through high resistance loads HR1 and HR2 in order to maintain a data-stored state latched by the flip-flop circuit which is constituted by driver transistors Q3 and Q4.
As described above, the high resistance load-type memory cell is constituted by four transistors Q1-Q4 and two high resistance loads HR1 and HR2. As shown in FIG. 26B, first, a region where four n-channel MOS transistors are formed is required to form a single high resistance load-type memory cell. High resistance loads HR are formed on two n-channel MOS transistors which constitute driver transistors Q3 and Q4. As shown in FIG. 26C, only a p-type well region is required in order to provide a high resistance load-type memory cell. Thus, area required for the memory cell is smaller than that for the CMOS-type memory cell in which both p-type well and n-type well must be formed in a memory cell. Accordingly, the high resistance load-type memory cell is advantageous in improving degree of integration of SRAM.
Meanwhile, in the high resistance load-type memory cell, current is supplied from power supply potential Vcc through high resistance loads HR1 and HR2 in order to maintain a data-stored state latched by the flip-flop circuit which is constituted by driver transistors Q3 and Q4. This current is desired to be small to suppress power consumption during standby. Therefore, electric resistance of the high resistance load must be made as large as possible. However, increase in resistance of the resistance load is limited, and current flowing through the high resistance load is required to be larger than leak current at the time when the transistor is off in order to maintain the data. On the other hand, in the CMOS-type memory cell, current is supplied from power supply potential Vcc through load transistors (p-channel MOS transistors) Q5 and Q6 in order to maintain a storage state of data latched by the flip-flop circuit. Accordingly, current consumption during standby can be reduced to a level of junction leak current. As has been described above, the high resistance load-type memory cell is advantageous in improving degree of integration of the SRAM, while the CMOS-type memory cell is advantageous in reducing current consumption for holding a storage state of data, that is, in suppressing power consumption during standby.
In view of the above description, such a structure as shown in FIGS. 27A and 27B of the CMOS-type memory cell which allows improvement in degree of integration of the SRAM has been proposed.
Referring to FIG. 25A, FIGS. 27A and 27B, a p-channel thin film transistor (TFT) instead of a bulk-type p-channel MOS transistor is used as load transistors Q5 and Q6. Therefore, as shown in FIG. 27A, a region where four n-channel MOS transistors are formed is required in order to form a single memory cell. The p-channel TFTs which constitute load transistors Q5 and Q6 are formed on the n-channel MOS transistors which constitute driver transistors Q3 and Q4. As shown in FIG. 27B, four bulk-type n-channel MOS transistors are formed in a p-type well region. Thus, when the p-channel TFT is used as a load transistor, only a p-type well region is required in order to form a single memory cell. Therefore, by using the p-channel TFT, area which is required for the CMOS-type memory cell can be reduced and a structure of the CMOS-type memory cell which is advantageous in improving degree of integration is provided.
A CMOS-type SRAM memory cell in which a p-channel TFT formed of a polysilicon layer is used as a load transistor such as shown in FIGS. 28 and 29 is disclosed, for example, in "ICD89-26", pp. 1-6.
Referring to FIGS. 28 and 29, an n-type well region 502 and a p-type well region 503 are formed on a p-type silicon substrate 501 in this order. An n.sup.+ impurity region 209 of an n-channel MOS transistor which constitutes a driver transistor or an access transistor is formed at p-type well region 503. An isolation oxide film 200 is formed to isolate the n-channel MOS transistors from each other. Gate electrodes 201 and 202 made of a first polysilicon layer is formed on p-type well region 503 with a gate insulating film 210 therebetween. These gate electrodes 201 and 202 form a gate of the access transistor or the driver transistor. A gate electrode 204 made of a second polysilicon layer is formed on gate electrodes 201 and 202 with an insulating film therebetween. Gate electrode 204 forms a gate of the p-channel TFT used as load transistors Q5 and Q6. A source region 206a, a channel region 206, and a drain region 206b of the TFT, which are made of third polysilicon layer, are formed on gate electrode 204 with a gate insulating film 212 therebetween. Source region 206a of the TFT forms a power supply interconnection Vcc. Drain region 206b of one TFT is connected to gate electrode 204 of the other TFT through a contact hole 205. An interlayer insulating film 214 is formed to cover each transistor. A refractory metal layer 207a is formed so as to be in contact with n.sup.+ impurity region 209 through a contact hole 208. An interlayer insulating film 216 is formed on refractory metal layer 207a. An aluminum metal layer 207b is connected to refractory metal layer 207a. A bit line is formed of aluminum metal layer 207b.
The present invention can be applied to manufacturing of any one of the above-described types of SRAMs, and in particular, it can be applied effectively to a high resistance load-type SRAM. Accordingly, application to the high resistance load-type SRAM will be mainly described in the following embodiments. A specific structure of the above-described conventional high resistance load-type SRAM will now be described somewhat in detail with reference to FIGS. 30-32. The conventional high resistance load-type SRAM with an equivalent circuit shown in FIG. 26A has such an arrangement as shown in FIG. 30 when it is viewed two-dimensionally. FIGS. 31 and 32 are cross sections taken along the lines X--X and Y--Y in FIG. 30, respectively.
Referring to FIG. 31, in this conventional high resistance load-type SRAM, a gate electrode 3 made of a first polycrystalline silicon layer is provided on a channel region sandwiched between n-type impurity diffusion layers 6 and 7 which constitute a drain region and a source region of driver transistor Q3 and which are formed at a surface of a semiconductor substrate 1, with a gate insulating film 2 therebetween. A gate electrode 5 made of the first polycrystalline silicon layer is also provided on a channel region sandwiched between n-type impurity diffusion layers 6 and 7 of driver transistor Q4 with gate insulating film 2 therebetween. High resistance loads 9 and 9 which are made of a second polycrystalline layer and constitute high resistance loads HR1 and HR2 are formed above gate electrodes 3 and 5, respectively. A pair of bit lines 10 and 10 are formed on high resistance loads 9 and 9 with an interlayer insulating film 8 therebetween.
Referring to FIG. 32, an access transistor Q1 is provided with a gate electrode 11 made of the first polycrystalline silicon layer on a channel region sandwiched between n-type impurity diffusion layers 7 and 7 which constitute a source region and a drain region of access transistor Q1, with a gate insulting film therebetween. Bit line 10 is electrically connected to one n-type impurity diffusion layer 7 at a contact 14 through a contact hole 14a which is formed in interlayer insulating film 8. First gate electrode 3 and one high resistance load 9 are joined to each other on a region of the other n-type impurity diffusion layer 7 of access transistor Q1, and high resistance load 9 is electrically connected to n-type impurity diffusion layer 7 at a contact 13 (see FIG. 30).
The pair of high resistance loads 9 and 9 are formed so as to have high resistance not across their entire length, but at a prescribed region thereof.
Gate electrode 5 of driver transistor Q4 and impurity diffusion layer 7 which forms the drain region of driver transistor Q3 are electrically connected to each other at a contact hole 17. A pair of bit lines 10 and 10 are formed by patterning a first aluminum interconnection layer.
In the above-described conventional high resistance load-type SRAM memory cell, a single memory is constituted by six elements including four MOS-type transistors and two high resistance loads. Although area required for the memory cell has been reduced by placing a high resistance load above a driver transistor, prescribed spaces are necessary to isolate n-type impurity diffusion layers which constitute source and drain regions of each transistor from each other and to isolate three gate electrodes which has been formed by patterning a first polysilicon layer from each other, and therefore, it has been very difficult to reduce area required for the memory cell. Accordingly, implementation of a high resistance load-type SRAM which solves such a problem and has desired degree of integration requires more complex manufacturing process, which leads to increase in manufacturing cost.
Such conventional problems of the SRAM as described above relate not only to the high resistance load-type SRAM but also to a TFT-type SRAM in which a thin film transistor (TFT) instead of a high-resistance load is used as a load element, since a basic structure of the TFT-type SRAM is the same as that of the high resistance load-type SRAM.
In addition, although description of a structure which includes two polycrystalline silicon layers and one aluminum interconnection layer has been given in the conventional example above, a recently-disclosed structure including three or four polycrystalline silicon layers and two aluminum interconnection layers has similar problems since the basic structure thereof is the same as that of the conventional example.